Processing and/or control systems often use RISC microprocessors that generally use a bus architecture. The bus architecture includes a first high speed multi-master primary bus, which is often referred to as AHB, ASB or another acronym or abbreviation. Fast peripherals, typically memory devices such as nonvolatile memory and RAM, for example, may be coupled to the high speed primary bus through appropriate interfaces. The bus architecture also includes at least a secondary bus, which is often referred to as APB or another acronym or abbreviation. The secondary bus is coupled to the primary bus through an appropriate interface, and relatively slow peripherals such as input/output circuits and the like are coupled to the secondary bus.
A typical architecture of a RISC microprocessor system is shown in FIG. 1. The processor, which in the depicted example is an ARM7 processor, usually has its own bus NATIVE that is interfaced with the high speed primary bus AHB by the block AHB TO NATIVE. This transformed bus supports an appropriate protocol for managing the different information transfer functions that take place through the high speed primary bus AHB.
Typically, the high speed primary bus AHB is a multi-master bus, that is, the control of the bus may be taken by more than one master device. Typically, the high speed primary bus AHB may be controlled by the ARM7 processor, and also by a direct memory access (DMA) controller. The DMA controller may be used for accessing data stored in the memory devices coupled to the primary bus AHB, or for writing data therein based upon peripherals connected to the secondary bus APB. Control of the high speed primary bus AHB by the ARM7 processor or by the DMA controller is managed by an appropriate arbiter circuit ARBITER for preventing conflicts.
As schematically shown in FIG. 2 by the arrows, each data transfer from a peripheral coupled to the secondary bus APB to a peripheral coupled to the primary bus AHB through the DMA controller engages the high speed bus AHB for two transfer cycles or phases. This is regardless of whether there is a transfer of data from the peripheral to the memory or vice versa.
The steps for a DMA transfer are as follows:
1) a certain peripheral sends to the DMA controller a request for a data transfer in a DMA mode;
2) the DMA controller demands to the circuit ARBITER control of the high speed primary bus AHB (a clock cycle);
3) in the case of a data transfer from the peripheral to the RAM memory, the DMA controller reads the data register of the peripheral and writes the read data in a DMA buffer, wherein the high speed primary bus AHB and the secondary bus APB are both used;
4) the DMA controller processes the data (a clock cycle);
5) the DMA controller writes the data in the RAM memory, wherein the high speed primary bus AHB is used and any other master device (e.g., the ARM7 processor) is prevented from accessing the secondary bus APB; and
6) the DMA controller releases control of the high speed primary bus AHB.
The above example is only one of many possible examples for different bus architectures that require access to the primary bus in two transfer phases to complete a DMA data transfer.